Technical Field
The disclosure is related to display technology field, and more particular to a manufacturing method and a structure thereof of a TFT backplane.
Related Art
In display technology field, the flat panel display technology of a liquid crystal display (LCD) and organic light emitting diode display (OLED) and so on have been gradually replaced the CRT display. OLED has the advantages of self-luminous, low driving voltage, high luminous efficiency, short response time, high definition and contrast ratio, viewing angle of about 180°, wide usage temperature range, flexible display and large-area full color display. Thus OLED has been recognized as a display device with the most development potential.
OLED can be divided into the passive OLED (PMOLED) and active OLED (AMOLED) according to the drive types. AMOLED is a self-luminous component which is usually composed of a low temperature polysilicon (LTPS) TFT backplane and an electrical excitation light layer. Low temperature polysilicon has high electron mobility, stronger driving ability, and for the AMOLED, the use of low temperature polysilicon material has the advantages of high resolution, fast response, high brightness, high aperture ratio, low power consumption and so on.
The common processes for manufacturing the low temperature polysilicon are mainly the excimer laser annealing (ELA), solid phase crystallization (SPC) and so on, wherein, because the size can be increased easily and a cost advantage is higher, the SPC technique becomes a research hotspot. The SPC technique is divided into by way of directly heating and baking at a high temperature for a long time and by way of ion-induced. The way of ion-induced is adapted to implant the particular ion to induce an amorphous silicon layer.
The traditional manufacturing method of the TFT backplane based on the SPC technique generally includes the following steps of:
step 1, as shown in FIG. 1, providing a substrate 100, and depositing, in turn, a buffer layer 200 and a amorphous silicon (a-Si) layer 300 on the substrate 100;
step 2, as shown in FIG. 2, implanting an induced ion into the amorphous silicon (a-Si) layer 300 and performing a high-temperature baking, such that the amorphous silicon performs the crystallization rapidly to generate the polysilicon layer 300′, wherein the upper layer portion 310 of the polysilicon layer 300′ has more implanted induced ions and a lower layer portion 320 has a semiconductor layer with more pure polysilicon;
step 3, as shown in FIG. 3, etching the upper layer portion 310 of the polysilicon layer 300′, and retaining a semiconductor layer 320 with more pure polysilicon;
step 4, as shown in FIG. 4, patterning the semiconductor layer 320 using one mask to form an island active layer 400;
step 5, as shown in FIG. 5, coating a photoresist and patterning the photoresist using one mask, and then making the photoresist pattern 500 as a shielding layer to implant a doped ion into the island active layer 400, such that two sides of the island active layer 400 with implanted doped ion forms a source/drain contact region 401, and a middle portion of the island active layer 400 with no implanted doped ion forms a channel region 402;
step 6, as shown in FIGS. 6 and 7, removing the photoresist pattern 500 and then forming, in turn, a gate insulation layer 700, a gate 800, a insulation layer between the layers 900 and a source/drain 1000, the source/drain 1000 contacts with a source/drain contact region 401, so as to achieve the manufacture of the low temperature polysilicon TFT backplane.
It shows that in the manufacturing method of the TFT backplane based on the SPC technique, after implanting the induced ion to make the amorphous silicon crystallization to form the polysilicon layer 300′, it has to etch the upper layer portion 310 with more implanted induced ions to retain the semiconductor 320 with more pure polysilicon; then, it patterns the semiconductor 320 using one mask to form the island active layer 400; because of the need for forming the source/drain contact region 401, it is necessary to use one mask to form the photoresist pattern 500, and make the photoresist pattern 500 as the shielding layer to implant a doped ion into two sides of the island active layer 400, so as to form the source/drain contact region 401. This process not only needs a larger number of masks, but also requires two ion implantations, such that the production cost is higher.